The present disclosure relates to a variable-resistance memory device employing memory cells each including a storage element having a resistance varying in accordance with a voltage applied to the storage element and an access transistor connected in series to the storage element. The present disclosure also relates to a method for driving the variable-resistance memory device.
As described in documents such as K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada and H. Narisawa: ‘A Novel Resistance Memory with High Scalability and Nanosecond Switching’, Technical Digest IEDM 2007, pp. 783-786, there is known a variable-resistance memory device employing memory cells each including a storage element. In each of the memory cells, by injecting conductive ions into an insulation film of the storage element or extracting conductive ions from the insulation film, the resistance of the storage element can be changed.
The storage element has a structure created by laminating a conductive-ion supplying layer, which serves as a layer for supplying the conductive ions, on the insulation layer between two electrodes. The memory cells are each configured to have such a storage element and an access transistor connected to the storage element in series between first and second common lines which can be driven by adoption of an active-matrix method.
Since such a memory cell thus has one transistor T and one variable resistor R of the storage element, the variable-resistance memory device is one of current-driven memories of the 1T1R type. This variable-resistance memory device is referred to as a ReRAM.
In the ReRAM, the magnitude of the resistance of the storage element indicates whether data has been written into the storage element or deleted from the storage element. A pulse with a short duration time of the nanosecond order can be used for carrying out an operation to write data into the storage element or erase data from the storage element. Thus, serving as an NVM (nonvolatile memory) capable of operating at a high speed like a RAM (Random Access Memory), the ReRAM draws much attention.
In a read or read-to-verify operation carried out on the ReRAM, a voltage is applied between the two electrodes of the storage element and a current flowing through the storage element as a result of applying the voltage is read out. In the following description, the read-to-verify operation is also referred to simply as a verify operation. The verify operation can be a verify operation carried out after an erase operation or a verify operation carried out after a write operation. However, the post-erase verify operation is basically the same as the post-write verify operation even though the polarity of the applied voltage in the former verify operation is different from the polarity of the applied voltage in the latter verify operation. That is to say, the direction of the flowing current in the post-erase verify operation is different from the direction of the flowing current in the post-write verify operation.
In addition, without regard to the type of the verify operation, it is necessary to limit the voltage applied in the verify operation to a relatively low read voltage VR in order to prevent a disturbance from occurring inadvertently. This is because an excessively large voltage applied in the verify operation may give rise to such a disturbance which causes data to be inadvertently erased from the storage element or inadvertently written into the storage element.
As a method for controlling a voltage applied to a bit line during a verify operation, there are known methods disclosed in Japanese patent Laid-open No. 2006-127672 (Patent Document 1) and Japanese patent Laid-open No. 2005-310196 (Patent Document 2) described below.
In accordance with the method disclosed in Patent Document 1, an NMOS transistor having a gate voltage set at VBIAS is provided on a read current path. The source electrode of the NMOS transistor is connected to the bit line in order to control the BL electric potential appearing on the bit line. At that time, the NMOS transistor operates as a source follower controlling the BL voltage to (VBIAS-Vgs) where symbol Vgs denotes a voltage appearing between the source and gate electrodes of the NMOS transistor.
In accordance with the method disclosed in Patent Document 2, on the other hand, a read voltage VR is generated as a fraction of a voltage obtained as a result of electrically charging a node determined in advance. The fraction is determined by a capacitance ratio. Then, in a state of dynamically holding the read voltage VR, a negative-feedback operational amplifier is used to clamp the BL voltage to the read voltage VR. That is to say, the negative-feedback operational amplifier operates as an amplifier for controlling the BL voltage to the read voltage VR. Thus, in accordance with the method disclosed in Patent Document 2, the magnitude of a cell current flowing through a memory cell is detected as a value determined by the following relation:Cell current=Read voltage VR/Storage-element resistance